1. Field of the Invention
The present disclosure relates to video signal decoding systems and methods for decoding video signals, and more particularly to video signal decoding systems and methods for decoding compressed high definition video signals incoming from different channels.
2. Description of the Related Art
Recently, as high definition (HD) digital broadcasting has been carried out, digital televisions having various functions have been developed. Some digital televisions have functions such as picture-in-picture (PIP) and double window display that use technology of decoding MPEG video streams incoming from different channels.
In order to decode MPEG video streams incoming from different channels, two discrete MPEG decoder chips have been used or an expensive MPEG decoder chip including two video decoders has been used.
FIG. 1 and FIG. 2 are block diagrams illustrating conventional video decoding systems for decoding and displaying two HD video signals, which are also disclosed in U.S. Patent Application Publication No. 2004-0028142. FIG. 1 shows a conventional video decoding system 10 for decoding and displaying two HD video signals. The conventional system 10 has two video decoders. Each of the video decoders included in the video decoding system 10 includes a buffer, a variable length decoder VLD, an inverse quantizer IQ, an inverse discrete cosine transformer IDCT and a motion compensation circuit MC. As exemplified by the system 10, when each of the video decoders has the same kind of building blocks arranged individually, the video decoding system may be simple but the video decoding system may have a large chip size when implemented on semiconductor integrated circuits.
FIG. 2 shows a conventional video decoding system 20 for decoding and displaying two HD video signals. The video decoding system 20 includes buffers 301 and 305, a variable length decoder 302 and a motion compensation circuit MC that are used commonly for the two compressed HD video signals incoming from different channels. Thus, the video decoding system 20 of FIG. 2 may have a relatively smaller chip size than the system 10 of FIG. 1 when implemented on semiconductor integrated circuits. Unfortunately, the video decoding system 20 still includes two inverse quantizers IQ and two inverse discrete cosine transformers IDCT for the two compressed HD video signals incoming from different channels.
Further, the conventional video decoding systems 10 and 20 shown in FIG. 1 and FIG. 2, respectively, perform signal processing on video streams with respect to pictures. Thus, the efficiency of time division is not high enough. In addition, in the conventional video decoding systems 10 and 20, the period of the decoding synchronization signal may be generated irregularly and the decoded video signal may be displayed irregularly when decoding is performed using a mixed mode of a frame picture and a field picture or using a 3:2 pull-down decoding, for example.